Semiconductor structure and method formation method thereof

ABSTRACT

A semiconductor structure and a formation method thereof are provided. The formation method includes: providing a substrate and a fin, a gate structure being formed on the substrate, the gate structure spanning the fin and covering a partial sidewall and a partial top of the fin, and a source/drain doping region being formed in the fin on both sides of the gate structure; forming a first dielectric layer on the substrate, the first dielectric layer exposing the top of the fin; forming an etch stop layer to conformally cover the first dielectric layer and the fin and the source/drain doping region exposed by the first dielectric layer; forming a second dielectric layer on the etch stop layer; and forming a conductive plug penetrating through the second dielectric layer and the etch stop layer, the conductive plug spanning the fin, and the conductive plug being connected to the source/drain doping region. Under the action of a first dielectric layer, the effective area between a conductive plug and a gate structure is reduced, and the parasitic capacitance between a conductive plug and a device gate structure is reduced accordingly.

RELATED APPLICATIONS

The present application claims priority to Chinese Patent Appln. No.201910577056.6, filed Jun. 28, 2019, the entire disclosure of which ishereby incorporated by reference.

BACKGROUND Technical Field

Embodiments and implementations of the present disclosure relate to thefield of semiconductor manufacturing, and in particular, to asemiconductor structure and a formation method thereof.

Related Art

In semiconductor manufacturing, in order to better adapt to reduction ofa feature size, semiconductor processes are beginning to transit from aplanar MOSFET to a more efficient three-dimensional transistors, such asa fin field effect transistor (FinFET). In the FinFET, a gate structuremay control an ultra-thin body (fin) from at least two sides. Comparedwith the planar MOSFET, the gate structure has stronger control abilityon a channel, and can well suppress a short channel effect; and theFinFET has better compatibility with existing integrated circuitmanufacturing than other devices.

After forming a semiconductor device, it is necessary to use a pluralityof metal layers to connect the semiconductor devices together to form acircuit. The metal layer includes an interconnect line and a conductiveplug (CT) formed in a contact hole, where the conductive plug in thecontact hole is connected to the semiconductor device, and theinterconnect line connects conductive plugs on different semiconductordevices to form a circuit. For example, a conductive plug in a fin fieldeffect transistor includes a conductive plug electrically connected to agate structure, and a conductive plug electrically connected to asource/drain doping region.

However, as device feature sizes continue to decrease, the size of thesource/drain doping region also decreases proportionally. Therefore, inorder to reduce the critical dimension (CD) and overlay precisionrequirements of a lithography process, a trench conductive plug (trenchCT) has been introduced. The fin field effect transistor (FinFET) istaken as an example. The trench conductive plug has a strip shape, whichextends in the same direction as an extending direction of a gatestructure and spans a fin.

SUMMARY

Embodiments and implementations of the present disclosure are directedto a semiconductor structure and a formation method thereof, whichimprove the performance of a semiconductor structure.

To address the aforementioned problem, embodiments and implementationsof the present disclosure provide a formation method of a semiconductorstructure. In one form, a formation method includes: providing asubstrate and a fin protruding from the substrate, where a gatestructure is formed on the substrate, the gate structure spanning thefin and covering a partial sidewall and a partial top of the fin, and asource/drain doping region is formed in the fin on both sides of thegate structure; forming, after forming the source/drain doping region, afirst dielectric layer on the substrate exposed by the fin, the firstdielectric layer exposing a top of the fin; forming an etch stop layer,the etch stop layer conformally covering the first dielectric layer andthe fin and the source/drain doping region exposed by the firstdielectric layer; forming a second dielectric layer on the etch stoplayer; and forming a conductive plug penetrating through the seconddielectric layer and the etch stop layer, the conductive plug spanningthe fin, and the conductive plug being connected to the source/draindoping region.

The present disclosure also provides a semiconductor structure. In oneform, a semiconductor structure includes: a substrate; a fin, protrudingfrom the substrate; a device gate structure, spanning the fin andcovering a partial sidewall and a partial top of the fin; a source/draindoping region, located in the fin on both sides of the device gatestructure; a first dielectric layer, located on the substrate exposed bythe fin, the first dielectric layer exposing a top of the fin; an etchstop layer, conformally covering the fin and the source/drain dopingregion exposed by the first dielectric layer, and the first dielectriclayer; a second dielectric layer, located on the etch stop layer, thesecond dielectric layer covering a sidewall of the device gatestructure; and a conductive plug, penetrating through the seconddielectric layer and the etch stop layer on both sides of the devicegate structure, the conductive plug spanning the fin, and the conductiveplug being connected to the source/drain doping region.

Compared with the prior art, technical solutions of embodiments andimplementations of the present disclosure have the following advantages:

In embodiments and implementations of the present disclosure, after asource/drain doping region is formed, a first dielectric layer is formedon a substrate exposed by a fin, the first dielectric layer exposing thefin; after the first dielectric layer is formed, an etch stop layer isformed, the etch stop layer conformally covering the fin and thesource/drain doping region exposed by the first dielectric layer and thefirst dielectric layer; a second dielectric layer is formed on the etchstop layer, and after a conductive plug penetrating through the seconddielectric layer and the etch stop layer is subsequently formed underthe action of the first dielectric layer, the height of the conductiveplug on both sides of the fin is reduced, thereby reducing the effectivearea between the conductive plug and a device gate structure, reducingthe parasitic capacitance between the conductive plug and the devicegate structure accordingly, and further improving the performance (e.g.,alternating current performance) of the semiconductor structure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1-FIG. 8 are schematic diagrams corresponding to various steps of amethod for forming a semiconductor structure.

FIG. 9-FIG. 24 are schematic diagrams corresponding to various steps inone form of a method for forming a semiconductor structure according tothe present disclosure.

DETAILED DESCRIPTION

The performance of current semiconductor structures may be furtherimproved. A formation method of a semiconductor structure is nowcombined to analyze the reasons for the performance to be improved.

FIG. 1-FIG. 8 are schematic diagrams corresponding to various steps of amethod for forming a semiconductor structure.

Referring to FIG. 1 and FIG. 2, FIG. 1 is a stereogram, and FIG. 2 is across-sectional view of FIG. 1 in a y1 y 2 direction. A substrate 10 anda fin 11 protruding from the substrate 10 are provided, where anisolating layer 15 is formed on the substrate 10 exposed by the fin 11,the isolating layer 15 covers a partial sidewall of the fin 11, a dummygate structure 20 is formed on the isolating layer 15, and the dummygate structure 20 spans the fin 11 and covers a partial sidewall and apartial top of the fin 11.

Referring to FIG. 3, FIG. 3 is a cross-sectional view based on FIG. 2,where a source/drain doping region 25 is formed in the fin 11 on bothsides of the dummy gate structure 20.

Referring to FIG. 4, an etch stop layer 35 is formed, the etch stoplayer 35 conformally covering the substrate 10, the fin 11, thesource/drain doping region 25, and the dummy gate structure 20.

Referring to FIG. 5, an interlayer dielectric layer 12 covering the etchstop layer 35 is formed, the interlayer dielectric layer 12 exposing thetop of the dummy gate structure 20.

In the process of forming the interlayer dielectric layer 12, the etchstop layer 35 on the top of the dummy gate structure 20 is removed.

Referring to FIG. 6, the dummy gate structure 20 (as shown in FIG. 5) isremoved, and a gate opening (not shown) is formed in the interlayerdielectric layer 12. A device gate structure 40 is formed in the gateopening.

Referring to FIG. 7, the device gate structure 40 of a partial thicknessis removed to form a groove (not shown) surrounded by the interlayerdielectric layer 12 and the remaining device gate structure 40. Aprotective layer 50 is formed in the groove.

Referring to FIG. 8, a trench is formed in the interlayer dielectriclayer 12 and the etch stop layer 35 between adjacent device gatestructures 40 by a self-aligned contact (SAC) etching process. Thetrench spans the fin 11, and the trench exposes the source/drain dopinglayer 25. A conductive plug 60 is formed in the trench.

The trench spans the fin 11, and thus the conductive plug 60 also spansthe fin 11. Correspondingly, the partial conductive plug 60 is locatedon the source/drain doping layer 25, and the partial conductive plug 60is located on the isolating layer 15. That is, the height of theconductive plug 60 on the isolating layer 15 is greater than the heightof the conductive plug 60 on the source/drain doping layer 25, such thatthe effective area between the conductive plug 60 and the device gatestructure 40 is large, resulting in a large parasitic capacitancebetween the conductive plug 60 and the device gate structure 40. Theperformance (e.g., alternating current performance) of the semiconductorstructure is further reduced. Moreover, the aforementioned problemsoccur not only in the self-aligned contact etching process, but also inthe non self-aligned contact (non-SAC) etching process.

To address the technical problem, in embodiments and implementations ofthe present disclosure, after a source/drain doping region is formed, afirst dielectric layer is formed on a substrate exposed by a fin, thefirst dielectric layer exposing the fin; after the first dielectriclayer is formed, an etch stop layer is formed, the etch stop layerconformally covers the fin and the source/drain doping region exposed bythe first dielectric layer and the first dielectric layer; a seconddielectric layer is formed on the etch stop layer, and after aconductive plug penetrating through the second dielectric layer and theetch stop layer is subsequently formed under the action of the firstdielectric layer, the height of the conductive plug on both sides of thefin is reduced, thereby reducing the effective area between theconductive plug and a device gate structure, reducing the parasiticcapacitance between the conductive plug and the device gate structureaccordingly, and further improving the performance (e.g., alternatingcurrent performance) of the semiconductor structure.

To make the above objects, features and advantages of the presentdisclosure more clearly understood, specific embodiments andimplementations of the present disclosure will be described in detailbelow with reference to the accompanying drawings.

FIG. 9-FIG. 24 are schematic diagrams corresponding to various steps inone form of a method for forming a semiconductor structure according tothe present disclosure.

Referring to FIG. 9 to FIG. 11, FIG. 9 is a stereogram, FIG. 10 is across-sectional view of FIG. 9 in a Y1Y2 direction, and FIG. 11 is across-sectional view of FIG. 9 in an X1X2 direction. A substrate 100 anda fin 110 protruding from the substrate 100 are provided, a gatestructure 200 is formed on the substrate 100, and the gate structure 200spans the fin 110 and covers a partial sidewall and a partial top of thefin 110.

The substrate 100 is used to provide a process platform for subsequentformation of a fin field effect transistor.

In some implementations, the substrate 100 is a silicon substrate. Inother implementations, the material of the substrate may also be othermaterials such as germanium, silicon germanide, silicon carbide, galliumarsenide or indium gallide, and the substrate can also be other types ofsubstrates such as a silicon substrate on an insulator or a germaniumsubstrate on an insulator.

The fin 110 is used to provide a channel for the formed fin field effecttransistor.

In some implementations, the fin 110 and the substrate 100 are of anintegrated structure. In other implementations, the fin may also be asemiconductor layer epitaxially grown on the substrate for the purposeof accurately controlling the fin height.

To this end, in some implementations, the material of the fin 110 is thesame as the material of the substrate 100, and the material of the fin110 is silicon. In other implementations, the material of the fin mayalso be a semiconductor material suitable for forming a fin, such asgermanium, silicon germanide, silicon carbide, gallium arsenide orindium gallide, and the material of the fin may also be different fromthe material of the substrate.

As shown in FIG. 11, in some implementations, an isolating layer 101 isformed on the substrate 100 exposed by the fin 110, and the isolatinglayer 101 covers a partial sidewall of the fin 110.

The isolating layer 101 serves as a shallow trench isolating structure(STI) for isolating adjacent devices. In some implementations, thematerial of the isolating layer 101 is silicon oxide. In otherimplementations, the material of the isolating layer may also be otherinsulating materials such as silicon nitride or silicon oxynitride.

In some implementations, the gate structure 200 is a dummy gatestructure. The gate structure 200 is used to occupy a spatial positionfor subsequent formation of a device gate structure.

In some implementations, for example, the gate structure 200 is asingle-layer structure, and the material of the gate structure 200 ispolysilicon. In other implementations, the material of the gatestructure may also be amorphous carbon. In still other implementations,the gate structure may also be a stacked structure including a dummygate oxide layer and a dummy gate layer on the dummy gate oxide layer.In other implementations, the gate structure may also be a device gatestructure for achieving normal transistor performance.

A gate mask layer 210 is formed on the top of the gate structure 200,the gate mask layer 210 being used as an etch mask for forming the gatestructure 200. In some implementations, the material of the gate masklayer 210 is silicon nitride.

In some implementations, after the gate structure 210 is formed, themethod further includes: forming a side wall (not shown) on a sidewallof the gate structure 200. The side wall is used to protect the sidewallof the gate structure 200, and is also used to define a formation regionof a subsequent source/drain doping region, such that the source anddrain doping region has a certain distance from the gate structure 200.

It is to be noted that, for convenience of illustration, the side wallis not shown in some implementations.

Referring to FIG. 12, after the gate structure 200 is formed, the methodfurther includes: forming a source/drain doping region 250 in the fin110 on both sides of the gate structure 200.

In some implementations, the step of forming the source/drain dopingregion 250 includes: forming a groove (not shown) in the fin 110 on bothsides of the gate structure 210, forming an epitaxial layer in thegroove by using a selective epitaxial growth process, and self-dopingions in situ during the formation of the epitaxial layer to form thesource/drain doping region 250.

In some implementations, for example, the formed semiconductor structureis a positive channel metal oxide semiconductor (PMOS) transistor. Thematerial of the source/drain doping region 250 is silicon germanidedoped with P-type ions. That is, the material of the epitaxial layer issilicon germanide. The epitaxial layer is used to provide a pressurestress effect on a channel region of the PMOS transistor, therebyincreasing the carrier mobility of the PMOS transistor. The P-type ionsinclude B, Ga or In.

In other implementations, the semiconductor structure may also be anegative channel metal oxide semiconductor (NMOS) transistor, and thematerial of the source/drain doping region is correspondingly siliconcarbide or silicon phosphide doped with N-type ions. That is, thematerial of the epitaxial layer is silicon carbide or silicon phosphide.The epitaxial layer is used to provide a tensile stress effect on achannel region of the NMOS transistor, thereby increasing the carriermobility of the NMOS transistor. The N-type ions include P, As or Sb.

Referring to FIG. 13 to FIG. 16, FIG. 13 is a cross-sectional view in anextending direction of a fin (shown in the Y1Y2 direction in FIG. 9) ata top position of a gate structure, FIG. 14 is a cross-sectional view inan extending direction of a fin (shown in the X1X2 direction in FIG. 9)on one side of a gate structure, FIG. 15 is a cross-sectional view basedon FIG. 13, and FIG. 16 is a cross-sectional view based on FIG. 14.After the source/drain doping region 250 is formed, a first dielectriclayer 112 (as shown in FIG. 16) is formed on the substrate 100 exposedby the fin 110, the first dielectric layer 112 exposing the top of thefin 110.

The first dielectric layer 112 is used to achieve electrical isolationbetween adjacent devices, and is also used to provide a process platformfor subsequent formation of an etch stop layer.

Therefore, the material of the first dielectric layer 112 is aninsulating material. In some implementations, the material of the firstdielectric layer 112 is silicon oxide. In other implementations, thematerial of the first dielectric layer may also be other insulatingmaterials such as silicon oxynitride.

In some implementations, the first dielectric layer 112 exposes the topof the fin 110, so that a subsequently formed etch stop layer can coverthe source/drain doping region 250, thereby enabling the etch stop layerto play a corresponding role in the subsequent process of forming aconductive plug. Moreover, the subsequently formed etch stop layer cancover the top of the fin 110 to protect the fin 110.

Specifically, the step of forming the first dielectric layer 112includes the following steps:

Referring to FIG. 13 and FIG. 14, a first dielectric material layer 102is formed on the substrate 100 exposed by the fin 110, where a top ofthe first dielectric material layer 102 is flush with the top of thegate structure 200.

The first dielectric material layer 102 is used to prepare forsubsequent formation of a first dielectric layer.

The surface flatness of the first dielectric layer is made higher byfirst forming the first dielectric material layer 102.

Specifically, the step of forming the first dielectric material layer102 includes: forming an initial first dielectric material layer (notshown) on the substrate 100 exposed by the fin 110, the initial firstdielectric material layer covering the gate mask layer 210 (as shown inFIG. 12); and planarizing the initial first dielectric material layer,and removing the initial first dielectric material layer above the topof the gate structure 200, the remaining initial first dielectricmaterial layer serving as the first dielectric material layer 102. Thegate mask layer 210 on the top of the gate structure 200 is also removedduring the planarization process.

In some implementations, the initial first dielectric material layer isplanarized by a chemical mechanical grinding process. In the step of thechemical mechanical grinding process, an end point detection (EPD) modemay be used, and the top of the gate structure 200 serves as a grindingstop position, so that the surface flatness of the first dielectricmaterial layer 102 is higher.

In other implementations, the initial first dielectric material layermay also be planarized with the top of the gate mask layer as a stopposition; and after the planarization process, the remaining initialfirst dielectric material layer and the gate mask layer are etched backuntil the top of the gate structure is exposed, and the remaininginitial first dielectric material layer after the etching process isused as the first dielectric material layer.

Referring to FIG. 15 and FIG. 16, the first dielectric material layer102 of a partial thickness is etched back to expose the top of the fin110, and the remaining first dielectric material layer 102 serves as thefirst dielectric layer 112.

In some implementations, the first dielectric material layer 102 of apartial thickness is etched back by using a dry etching process. The dryetching process has the characteristics of anisotropic etching, the topsurface position of the first dielectric layer 112 is easily controlledby using a dry etching process, and the surface flatness of the firstdielectric layer 112 can be improved.

In some implementations, after the first dielectric material layer 102of a partial thickness is etched back, the top of the first dielectriclayer 112 is flush with the top of the fin 110.

After a conductive plug is subsequently formed, the conductive plugspans the fin, and the conductive plug is electrically connected to thesource/drain doping region. Therefore, the top position of the firstdielectric layer 112 is used to define the bottom position of theconductive plug. The height of the conductive plug on both sides of thefin 110 can be significantly reduced by aligning the top of the firstdielectric layer 112 with the top of the fin 110.

In other implementations, the top of the first dielectric layer may alsobe below the top of the fin according to process requirements.

Referring to FIG. 17 and FIG. 18, FIG. 17 is a cross-sectional viewbased on FIG. 15, and FIG. 18 is a cross-sectional view based on FIG.16. An etch stop layer 300 is formed, the etch stop layer 300conformally covering the first dielectric layer 112 and the fin 110 andthe source/drain doping region 250 exposed by the first dielectric layer112.

The subsequent process further includes: forming a second dielectriclayer on the etch stop layer 300. The process of forming a conductiveplug includes: forming a trench by an etching process. The process offorming the trench includes the step of etching a second dielectriclayer, where the top of the etch stop layer 300 is used to define a stopposition of the etching process during the process of etching the seconddielectric layer.

Therefore, the material of the etch stop layer 300 includes at least oneof silicon nitride, silicon carbonitride, silicon carbide or siliconoxynitride. The aforementioned material is a dielectric material, whichhas high hardness and density, such that the etch stop layer 300 canplay a corresponding role.

In some implementations, the material of the etch stop layer 300 issilicon nitride.

Specifically, the etch stop layer 300 is formed by a chemical vapordeposition process.

Correspondingly, the etch stop layer 300 conformally covers the firstdielectric layer 112 and a dummy gate structure (i.e., the gatestructure 200), the fin 110 and the source/drain doping region 250exposed by the first dielectric layer 112.

Referring to FIG. 19 and FIG. 20, FIG. 19 is a cross-sectional viewbased on FIG. 17, and FIG. 20 is a cross-sectional view based on FIG.18. A second dielectric layer 103 is formed on the etch stop layer 300.

The second dielectric layer 103 is also used to achieve electricalisolation between adjacent devices, and is also used to provide aprocess basis for subsequent formation of a conductive plug.

Therefore, the material of the second dielectric layer 103 is aninsulating material.

In some implementations, the material of the second dielectric layer 103is silicon oxide. Silicon oxide is a material commonly used as adielectric layer in the field of semiconductors, which is low in processcost.

Moreover, the materials of the first dielectric layer 112 and the seconddielectric layer 103 are both silicon oxide, which significantlyalleviates the problem of stress between the first dielectric layer 112and the etch stop layer 300 and between the second dielectric layer 103and the etch stop layer 300, such that the adhesion between the firstdielectric layer 112 and the etch stop layer 300 and between the seconddielectric layer 103 and the etch stop layer 300 is better. A stableoxide-nitride-oxide (ONO) stacked structure is thus obtained.

In other implementations, the material of the second dielectric layermay also be other insulating materials such as silicon oxynitride.

In some implementations, the second dielectric layer 103 covers asidewall of the gate structure 200.

Specifically, the step of forming the second dielectric layer 103includes: forming a second dielectric material layer (not shown)covering the etch stop layer 300, planarizing the second dielectricmaterial layer, and removing the second dielectric material layer abovethe top of the etch stop layer 300, the remaining second dielectricmaterial layer serving as the second dielectric layer 103. The top ofthe etch stop layer 300 refers to the top of the etch stop layer 300 onthe top of the gate structure 200, i.e., the highest position in the topsurface of the etch stop layer 300.

The etch stop layer 300 has high hardness and density, and the surfaceflatness of the second dielectric layer 103 can be improved by using thetop of the etch stop layer 300 as a stop position of the planarizationprocess.

In some implementations, the second dielectric material layer isplanarized by a chemical mechanical grinding process. In the step of thechemical mechanical grinding process, an end point detection mode may beused, and the top of the etch stop layer 300 serves as a grinding stopposition. In other implementations, the planarization process may alsoinclude an etchback process and a chemical mechanical grinding processthat are performed sequentially.

In some implementations, the gate structure 200 is a dummy gatestructure. Therefore, referring to FIG. 21, FIG. 21 is a cross-sectionalview based on FIG. 19. The formation method further includes: removingthe gate structure 200 (as shown in FIG. 19), and forming a gate opening122 in the first dielectric layer 112 (as shown in FIG. 20) and thesecond dielectric layer 103.

The gate opening 122 is used to provide a spatial position forsubsequent formation of a gate structure. In some implementations, thegate structure 200 spans the fin 110, and therefore the gate opening 122exposes the partial top and the partial sidewall of the fin 110, andalso exposes the partial isolating layer 101.

In some implementations, the step of removing the gate structure 200includes: removing the gate structure 200 of a partial thickness using adry etching process; and removing the gate structure 200 of theremaining thickness using a wet etching process.

The dry etching process has the characteristics of anisotropic etching.By selecting the dry etching process, it is advantageous to obtain thegate opening 122 having a relatively vertical sidewall, and the removalefficiency of the gate structure 200 can be improved. The wet etchingprocess has the characteristics of isotropic etching, is easy to realizea higher etching selectivity ratio between different materials, and isadvantageous to completely remove the gate structure 200 of theremaining thickness and reduce damage to other film layers. Therefore,by combining the dry etching process and the wet etching process, theprocess of removing the gate structure 200 is prevented from causingdamage to other film layers while improving the removal efficiency ofthe gate structure 200. For example, the damage to the isolating layer101, the first dielectric layer 112 and the second dielectric layer 103can be reduced, and the performance of the device is correspondinglyimproved.

In other implementations, the gate structure may also be removed byusing the dry etching process.

It is to be noted that an etch stop layer 300 is further formed on thetop of the gate structure 200. Therefore, before removing the gatestructure 200, the method further includes: removing the etch stop layer300 on the top of the gate structure 200.

Specifically, the etch stop layer 300 on the top of the gate structure200 is removed by using the dry etching process.

Referring to FIG. 22, a device gate structure 400 is formed in the gateopening 122.

The device gate structure 400 is used to control the turn-on andturn-off of a channel region of a transistor.

In some implementations, the device gate structure 400 is a metal gatestructure. Therefore, the step of forming the device gate structure 400includes: forming a high-k gate dielectric layer 410 conformallycovering the bottom and sidewall of the gate opening 122; and after thehigh-k gate dielectric layer 410 is formed, filling a conductivematerial in the gate opening 122 to form a gate electrode layer 420.

The high-k gate dielectric layer 410 is used to achieve electricalisolation between the gate electrode layer 420 and a channel.

The material of the high-k gate dielectric layer 410 is a high-kdielectric material. The high-k dielectric material refers to adielectric material having a relative dielectric constant greater than arelative dielectric constant of silicon oxide. In some implementations,the material of the high-k gate dielectric layer 410 is HfO₂. In otherimplementations, the material of the high-k gate dielectric layer mayalso be selected from ZrO₂, HfSiO, HfS iON, HfTaO, HfTiO, HfZrO orAl₂O₃.

In other implementations, when the device gate structure is apolysilicon gate structure, the material of the gate dielectric layerincludes at least one of silicon oxide, silicon nitride, siliconoxynitride, silicon carbide, silicon carbonitride, or siliconoxycarbonitride.

The gate electrode layer 420 serves as an electrode for achieving anelectrical connection with an external circuit. In some implementations,the material of the gate electrode layer 420 is Al. In otherimplementations, the material of the gate electrode layer may also be W,Cu, Ag, Au, Pt, Ni or Ti.

It is to be noted that after forming the high-k gate dielectric layer410 and before forming the gate electrode layer 420, the step of formingthe device gate structure 400 further includes the step of forming afunctional layer such as a work function layer. For the convenience ofillustration, other functional layers are not illustrated in someimplementations.

Referring to FIG. 23 and FIG. 24, a conductive plug 500 (as shown inFIG. 24) is formed in the second dielectric layer 103 and the etch stoplayer 300 on both sides of the device gate structure 400, the conductiveplug 500 spanning the fin 110, and the conductive plug 500 beingconnected to the source/drain doping region 250.

The conductive plug 500 is used to achieve an electrical connectionbetween the source/drain doping region 250 and the external circuit.

In some implementations, the material of the conductive plug 500 is W.In other implementations, the material of the conductive plug may alsobe Al, Cu, Ag or Au.

In some implementations, the top position of the first dielectric layer112 is used to define the bottom position of the conductive plug 500.Under the action of the first dielectric layer 112, the height of theconductive plug 500 on both sides of the fin 110 is reduced, therebyreducing the effective area between the conductive plug 500 and thedevice gate structure 400, reducing the parasitic capacitance betweenthe conductive plug 500 and the device gate structure 400 accordingly,and further improving the performance (e.g., alternating currentperformance) of the semiconductor structure.

In some implementations, the conductive plug 500 is formed by using anon self-aligned contact etching process. That is, a formation positionof the conductive plug 500 is defined by a mask opening formed in a masklayer, and the mask opening is located on either side of the device gatestructure 400.

Specifically, the step of forming the conductive plug 500 includes thefollowing steps:

As shown in FIG. 23, a trench 550 exposing the source/drain dopingregion 250 and the first electric layer 112 is formed in the seconddielectric layer 103 and the etch stop layer 300 by using a nonself-aligned contact etching process, where an extending direction ofthe trench 550 is perpendicular to an extending direction of the fin110, and the trench 550 spans the fin 110.

The trench 550 is used to provide a spatial location for subsequentformation of the conductive plug.

Specifically, a mask layer 600 is formed on the gate structure 400 andthe second dielectric layer 103. A mask opening 610 exposing the partialsecond dielectric layer 103 on both sides of the gate structure 400 isformed in the mask layer 600. An extending direction of the mask opening610 is parallel to an extending direction of the gate structure 400, andthe mask opening 610 spans the fin 110. The mask layer 600 is used as amask to sequentially etch the second dielectric layer 103 and the etchstop layer 300 exposed by the mask opening 610 to form a trench 550exposing the source/drain doping region 250 and the first dielectriclayer 112 (as shown in FIG. 20).

In some implementations, the mask opening 610 spans the fin 110, andtherefore the trench 550 spans the fin 110 and exposes the source/draindoping region 250 and the first dielectric layer 112 on both sides ofthe fin 110.

With respect to the solution where a first dielectric layer is notformed, in some implementations, the trench 550 exposes the source/draindoping region 250 and the first dielectric layer 112, and the depth ofthe trench 550 above the source/drain doping region 250 is close to thedepth of the trench 550 above the first dielectric layer 112, which isadvantageous to reduce the probability of etch loss of the source/draindoping region 250, thereby increasing the process window for forming thetrench 550.

Moreover, some implementations of the present disclosure do not need toremove the device gate structure 400 of a partial thickness as comparedwith the solution of using a self-aligned contact etching process, andtherefore, the height of the device gate structure 400 is smaller, whichcorrespondingly reduces the difficulty of the etching process usedduring the formation of the gate structure 200.

In addition, since the height of the device gate structure 400 issmaller, in the photolithography process of forming the trench 550, alithography device is more likely to achieve alignment, therebyfacilitating improvement of the overlay (OVL) precision.

The etch stop layer 300 also covers a sidewall of the device gatestructure 400, the etch stop layer 300 being capable of protecting thesidewall of the device gate structure 400 during formation of the trench550, so as to reduce the probability of the non self-aligned contactetching process causing erroneous etching of the device gate structure400.

In some implementations, the trench 550 is formed by etching using thedry etching process. Specifically, in the process of forming the trench550, the mask layer 600 is used as a mask, and the surface of the etchstop layer 300 is used as a stop position. The second dielectric layer103 exposed by the mask opening 610 is etched to form an initial trench,and then the etch stop layer 300 exposed by the initial trench isetched.

In some implementations, the mask layer 600 is a photoresist layer.After the trench 550 is formed, the mask layer 600 is removed in anashing or wet-process photoresist-removing manner.

It is to be noted that, after forming the second dielectric layer 103,the method further includes: forming a third dielectric layer 104covering the second dielectric layer 103. Correspondingly, the masklayer 600 is formed on the third dielectric layer 104. Before etchingthe second dielectric layer 103 exposed by the mask opening 610, themethod further includes: etching the third dielectric layer 104 exposedby the mask opening 610.

The third dielectric layer 104 is also used to achieve electricalisolation between adjacent devices. Moreover, the third dielectric layer104 is also used to provide a process platform for forming a conductiveplug electrically connected to the device gate structure 400.

Therefore, the material of the third dielectric layer 104 is aninsulating material. In some implementations, the material of the thirddielectric layer 104 is silicon oxide. The material of the thirddielectric layer 104 is the same as that of the first dielectric layer112 and the second dielectric layer 103, thereby reducing the complexityof the etching process. In other implementations, the material of thethird dielectric layer may also be other insulating materials such assilicon oxynitride.

Referring to FIG. 24, the trench 550 (as shown in FIG. 23) is filled toform the conductive plug 500.

The conductive plug 500 is electrically connected to the source/draindoping layer 250 for electrically connecting the source/drain dopinglayer 250 to the external circuit.

In some implementations, the material of the source/drain doping layer250 is W. W has the advantages of high melting point, good thermalstability, good electrical conductivity, strong step coverage, andstrong electromigration resistance. By selecting a W material, it isadvantageous to improve the performance of a device. Moreover, thethermal expansion coefficient of W is similar to that of Si. Therefore,it is also advantageous to reduce the stress in the conductive plug 500.In other implementations, the material of the conductive plug may alsobe a conductive material such as Al, Cu, Ag or Au.

Specifically, the step of forming the conductive plug 500 includes:filling the trench 550 with a conductive material, the conductivematerial also covering the top of the third dielectric layer 104; andplanarizing the conductive material, removing the conductive materialabove the top of the third dielectric layer 104, and retaining theconductive material in the trench 550 as the conductive plug 500.

In some implementations, the trench 550 is filled with a conductivematerial by using a chemical vapor deposition process. By using thechemical vapor deposition process, it is advantageous to increase thefilling ability of the conductive material, and it is advantageous toreduce the stress in the conductive plug 500. In other implementations,the conductive plug may also be formed by a physical vapor depositionprocess, a sputtering process, or an electroplating process.

In some implementations, the conductive material is planarized by usinga chemical mechanical grinding process, thereby improving the surfaceflatness of the conductive plug 500, and enabling the top of theconductive plug 500 to be flush with the top of the third dielectriclayer 104.

The present disclosure further provides a semiconductor structure.Referring to FIG. 24, FIG. 24 is a cross-sectional view in an extendingdirection (shown in the Y1Y2 direction in FIG. 9) of a fin at a topposition of a gate structure, and a schematic structural diagram of oneform of a semiconductor structure according to the present disclosure isshown.

The semiconductor structure includes: a substrate 100; a fin 110,protruding from the substrate 100; a device gate structure 400, spanningthe fin 110 and covering a partial sidewall and a partial top of the fin110; a source/drain doping region 250, located in the fin 110 on bothsides of the device gate structure 400; a first dielectric layer 112 (asshown in FIG. 20), located on the substrate 100 exposed by the fin 110,the first dielectric layer 112 exposing the top of the fin 110; an etchstop layer 300, conformally covering the fin 110 and the source/draindoping region 250 exposed by the first dielectric layer 112, and thefirst dielectric layer 112; a second dielectric layer 103, located onthe etch stop layer 300, the second dielectric layer 103 covering asidewall of the device gate structure 400; and a conductive plug 500,penetrating through the second dielectric layer 103 and the etch stoplayer 300 on both sides of the device gate structure 400, the conductiveplug 500 spanning the fin 110, and the conductive plug 500 beingconnected to the source/drain doping region 250.

The top position of the first dielectric layer 112 is used to define thebottom position of the conductive plug 500. Under the action of thefirst dielectric layer 112, the height of the conductive plug 500 abovethe source/drain doping region 250 is close to the height of theconductive plug 500 on both sides of the fin 110, so that the height ofthe conductive plug 500 on both sides of the fin 110 is reduced, therebyreducing the effective area between the conductive plug 500 and thedevice gate structure 400, reducing the parasitic capacitance betweenthe conductive plug 500 and the device gate structure 400 accordingly,and further improving the performance (e.g., alternating currentperformance) of the semiconductor structure.

In some implementations, the substrate 100 is a silicon substrate. Inother implementations, the material of the substrate may also be othermaterials such as germanium, silicon germanide, silicon carbide, galliumarsenide or indium gallide, and the substrate can also be other types ofsubstrates such as a silicon substrate on an insulator or a germaniumsubstrate on an insulator.

The fin 110 is used to provide a channel for the fin field effecttransistor.

In some implementations, the fin 110 and the substrate 100 are of anintegrated structure. In other implementations, the fin may also be asemiconductor layer epitaxially grown on the substrate for the purposeof accurately controlling the fin height.

To this end, in some implementations, the material of the fin 110 is thesame as the material of the substrate 100, and the material of the fin110 is silicon. In other implementations, the material of the fin mayalso be a semiconductor material suitable for forming a fin, such asgermanium, silicon germanide, silicon carbide, gallium arsenide orindium gallide, and the material of the fin may also be different fromthe material of the substrate.

As shown in FIG. 20, FIG. 20 is a cross-sectional view in a directionperpendicular to an extending direction (as shown in the X1X2 directionin FIG. 9) of a fin on one side of a device gate structure. In someimplementations, an isolating layer 101 is formed on the substrate 100exposed by the fin 110, and the isolating layer 101 covers a partialsidewall of the fin 110.

The isolating layer 101 serves as a shallow trench isolating structurefor isolating adjacent devices. In some implementations, the material ofthe isolating layer 101 is silicon oxide. In other implementations, thematerial of the isolating layer may also be other insulating materialssuch as silicon nitride or silicon oxynitride.

The device gate structure 400 is used to control the turn-on andturn-off of a channel region of a transistor.

In some implementations, the device gate structure 400 is a metal gatestructure. Therefore, the device gate structure 400 includes: a high-kgate dielectric layer 410 and a gate electrode layer 420 covering thehigh-k gate dielectric layer 410.

The high-k gate dielectric layer 410 is used to achieve electricalisolation between the gate electrode layer 420 and a channel.

The material of the high-k gate dielectric layer 410 is a high-kdielectric material. The high-k dielectric material refers to adielectric material having a relative dielectric constant greater than arelative dielectric constant of silicon oxide. In some implementations,the material of the high-k gate dielectric layer 410 is HfO₂. In otherimplementations, the material of the high-k gate dielectric layer mayalso be selected from ZrO₂, HfSiO, HfS iON, HfTaO, HfTiO, HfZrO orAl₂O₃.

In other implementations, when the device gate structure is apolysilicon gate structure, the material of the gate dielectric layerincludes one or more of silicon oxide, silicon nitride, siliconoxynitride, silicon carbide, silicon carbonitride, and siliconoxycarbonitride.

The gate electrode layer 420 serves as an electrode for achieving anelectrical connection with an external circuit. In some implementations,the material of the gate electrode layer 420 is Al. In otherimplementations, the material of the gate electrode layer may also be W,Cu, Ag, Au, Pt, Ni or Ti.

It is to be noted that a functional layer such as a work function layeris also formed between the high-k gate dielectric layer 410 and the gateelectrode layer 420. For the convenience of illustration, otherfunctional layers are not illustrated in some implementations.

In some implementations, a side wall (not shown) is further formed on asidewall of the device gate structure 400. The side wall is used toprotect the sidewall of the device gate structure 400, and is also usedto define a formation region of the source/drain doping region 250, suchthat the source and drain doping region 250 has a certain distance fromthe device gate structure 400.

It is to be noted that, for convenience of illustration, the side wallis not shown in some implementations.

The source/drain doping region 250 includes an epitaxial layer dopedwith conductive ions.

In some implementations, for example, the semiconductor structure is aPMOS transistor. The material of the source/drain doping region 250 issilicon germanide doped with P-type ions. That is, the material of theepitaxial layer is silicon germanide. The epitaxial layer is used toprovide a pressure stress effect on a channel region of the PMOStransistor, thereby increasing the carrier mobility of the PMOStransistor. The P-type ions include B, Ga or In.

In other implementations, the semiconductor structure may also be anNMOS transistor, and the material of the source/drain doping region iscorrespondingly silicon carbide or silicon phosphide doped with N-typeions. That is, the material of the epitaxial layer is silicon carbide orsilicon phosphide. The epitaxial layer is used to provide a tensilestress effect on a channel region of the NMOS transistor, therebyincreasing the carrier mobility of the NMOS transistor. The N-type ionsinclude P, As or Sb.

The first dielectric layer 112 is used to achieve electrical isolationbetween adjacent devices, and is also used to provide a process platformfor forming an etch stop layer 300. Therefore, the material of the firstdielectric layer 112 is an insulating material. In some implementations,the material of the first dielectric layer 112 is silicon oxide. Inother implementations, the material of the first dielectric layer mayalso be other insulating materials such as silicon oxynitride.

In some implementations, the first dielectric layer 112 exposes the topof the fin 110, so that the etch stop layer 300 can cover thesource/drain doping region 250, thereby enabling the etch stop layer 300to play a corresponding role in the process of forming a conductive plug500. Moreover, the etch stop layer 300 can cover the fin 110 to protectthe top of the fin 110.

In some implementations, the top of the first dielectric layer 112 isflush with the top of the fin 110. The conductive plug 500 spans the fin110, and the conductive plug 500 is electrically connected to thesource/drain doping region 250. Therefore, the top position of the firstdielectric layer 112 is used to define the bottom position of theconductive plug 500. The height of the conductive plug 500 on both sidesof the fin 110 can be significantly reduced by aligning the top of thefirst dielectric layer 112 with the top of the fin 110. In otherimplementations, the top of the first dielectric layer may also be belowthe top of the fin according to process requirements.

The process of forming the conductive plug 500 includes: forming atrench by an etching process. The process of forming the trench includesthe step of etching a second dielectric layer 103, where the top of theetch stop layer 300 is used to define a stop position of the etchingprocess during the process of etching the second dielectric layer 103,thereby reducing the probability of over-etching the first dielectriclayer 112 and causing etch damage to the source/drain doping region 250.

Therefore, the material of the etch stop layer 300 includes one or moreof silicon nitride, silicon carbonitride, silicon carbide and siliconoxynitride. The aforementioned material is a dielectric material, whichhas high hardness and density, such that the etch stop layer 300 canplay a corresponding role. In some implementations, the material of theetch stop layer 300 is silicon nitride.

In some implementations, the etch stop layer 300 also covers thesidewall of the device gate structure 400. The etch stop layer 300protects the sidewall of the device gate structure 400, so as to reducethe probability of damage to the device gate structure 400 caused by theprocess of forming the conductive plug 500.

The second dielectric layer 103 is also used to achieve electricalisolation between adjacent devices. Therefore, the material of thesecond dielectric layer 103 is an insulating material.

In some implementations, the material of the second dielectric layer 103is silicon oxide. Silicon oxide is a material commonly used as adielectric layer in the field of semiconductors, which is low in processcost. Moreover, the materials of the first dielectric layer 112 and thesecond dielectric layer 103 are both silicon oxide, which significantlyalleviates the problem of stress between the first dielectric layer 112and the etch stop layer 300 and between the second dielectric layer 103and the etch stop layer 300, such that the adhesion between the firstdielectric layer 112 and the etch stop layer 300 and between the seconddielectric layer 103 and the etch stop layer 300 is better. A stable ONOstacked structure is thus obtained.

In other implementations, the material of the second dielectric layermay also be other insulating materials such as silicon oxynitride.

It is also to be noted that the semiconductor structure furtherincludes: a third dielectric layer 104 located on the second dielectriclayer 103. The third dielectric layer 104 is also used to achieveelectrical isolation between adjacent devices. Moreover, the thirddielectric layer 104 is used to provide a process platform for forming aconductive plug electrically connected to the device gate structure 400.

Therefore, the material of the third dielectric layer 104 is aninsulating material. In some implementations, the material of the thirddielectric layer 104 is silicon oxide. The material of the thirddielectric layer 104 is the same as that of the first dielectric layer112 and the second dielectric layer 103, thereby reducing the complexityof the etching process. In other implementations, the material of thethird dielectric layer may also be other insulating materials such assilicon oxynitride.

The conductive plug 500 is used to achieve an electrical connectionbetween the source/drain doping region 250 and the external circuit.

In some implementations, the material of the conductive plug 500 is W.In other implementations, the material of the conductive plug may alsobe Al, Cu, Ag or Au.

Specifically, the conductive plug 500 penetrates through the thirddielectric layer 104, the second dielectric layer 103 and the etch stoplayer 300 on both sides of the device gate structure 400.

The semiconductor structure may be formed by implementations of themethod for forming a semiconductor structure described above, or mayalso be formed by other formation methods. For a detailed description ofthe semiconductor structure in some implementations, reference may bemade to the corresponding description in the foregoing embodiments andimplementations, and the descriptions are omitted here in someimplementations.

Although the present disclosure is disclosed above, the presentdisclosure is not limited thereto. Any person skilled in the art canmake various changes and modifications without departing from the spiritand scope of the present disclosure, and the scope of the presentdisclosure should be determined by the scope defined by the claims.

What is claimed is:
 1. A method for forming a semiconductor structure,comprising: providing a substrate and a fin protruding from thesubstrate, wherein a gate structure is formed on the substrate such thatthe gate structure spans the fin and covers a partial sidewall and apartial top of the fin, and a source/drain doping region is formed inthe fin on both sides of the gate structure; forming, after forming thesource/drain doping region, a first dielectric layer on the substrateexposed by the fin, where the first dielectric layer exposes a top ofthe fin; forming an etch stop layer, the etch stop layer conformallycovering the first dielectric layer and the fin and the source/draindoping region exposed by the first dielectric layer; forming a seconddielectric layer on the etch stop layer; and forming a conductive plugpenetrating through the second dielectric layer and the etch stop layer,the conductive plug spanning the fin, and the conductive plug beingconnected to the source/drain doping region.
 2. The method for forming asemiconductor structure according to claim 1, wherein the step offorming the first dielectric layer comprises: forming a first dielectricmaterial layer on the substrate exposed by the fin, where a top of thefirst dielectric material layer is flush with a top of the gatestructure; and etching back the first dielectric material layer of apartial thickness to expose the top of the fin.
 3. The method forforming a semiconductor structure according to claim 2, wherein thefirst dielectric material layer of a partial thickness is etched backusing a dry etching process.
 4. The method for forming a semiconductorstructure according to claim 1, wherein in the step of forming the firstdielectric layer, the top of the first dielectric layer is flush withthe top of the fin.
 5. The method for forming a semiconductor structureaccording to claim 1, wherein: the gate structure is a dummy gatestructure; in the step of forming a second dielectric layer on the etchstop layer, the second dielectric layer covers a sidewall of the gatestructure; and the method further comprises: after forming a seconddielectric layer on the etch stop layer and before forming a conductiveplug penetrating through the second dielectric layer and the etch stoplayer, removing the gate structure, forming a gate opening in the firstdielectric layer and the second dielectric layer, and forming a devicegate structure in the gate opening.
 6. The method for forming asemiconductor structure according to claim 5, wherein: in the step offorming the etch stop layer, the etch stop layer conformally covers thefirst dielectric layer and the gate structure, the fin and thesource/drain doping region exposed by the first dielectric layer; thestep of forming the second dielectric layer comprises: forming a seconddielectric material layer covering the etch stop layer, planarizing thesecond dielectric material layer, and removing the second dielectricmaterial layer above the top of the etch stop layer, the remainingsecond dielectric material layer serving as the second dielectric layer;and the method further comprises: after forming the second dielectriclayer and before removing the gate structure, removing the etch stoplayer on the top of the gate structure.
 7. The method for forming asemiconductor structure according to claim 1, wherein the step offorming the conductive plug comprises: forming a trench in the seconddielectric layer and the etch stop layer using a non self-alignedcontact etching process, wherein the trench exposes the source/draindoping region and the first electric layer, an extending direction ofthe trench is perpendicular to an extending direction of the fin, andthe trench spans the fin; and filling the trench to form the conductiveplug.
 8. The method for forming a semiconductor structure according toclaim 6, wherein the second dielectric material layer is planarizedusing a chemical mechanical grinding process.
 9. The method for forminga semiconductor structure according to claim 1, wherein the material ofthe etch stop layer comprises at least one of silicon nitride, siliconcarbonitride, silicon carbide or silicon oxynitride.
 10. The method forforming a semiconductor structure according to claim 1, wherein thematerial of the second dielectric layer and the material of the firstdielectric layer are silicon oxide.
 11. A semiconductor structure,comprising: a substrate; a fin, protruding from the substrate; a devicegate structure, spanning the fin and covering a partial sidewall and apartial top of the fin; a source/drain doping region, located in the finon both sides of the device gate structure; a first dielectric layer,located on the substrate exposed by the fin, the first dielectric layerexposing a top of the fin; an etch stop layer, conformally covering thefin and the source/drain doping region exposed by the first dielectriclayer, and the first dielectric layer; a second dielectric layer,located on the etch stop layer, the second dielectric layer covering asidewall of the device gate structure; and a conductive plug,penetrating through the second dielectric layer and the etch stop layeron both sides of the device gate structure, the conductive plug spanningthe fin, and the conductive plug being connected to the source/draindoping region.
 12. The semiconductor structure according to claim 11,wherein a top of the first dielectric layer is flush with the top of thefin.
 13. The semiconductor structure according to claim 11, wherein theetch stop layer also covers the sidewall of the device gate structure.14. The semiconductor structure according to claim 11, wherein thematerial of the etch stop layer comprises one or more of siliconnitride, silicon carbonitride, silicon carbide and silicon oxynitride.15. The semiconductor structure according to claim 11, wherein thematerial of the second dielectric layer and the material of the firstdielectric layer are silicon oxide.